イベントトップに戻る

セミナー一覧

12/15(木) 13:00 - 16:20 Advanced Packaging and Chiplet Summit 2022

12 /15(木)
Super THEATER
APCS

Advanced Packaging and Chiplet Summit 2022

グローバルリーダーによるパッケージングの未来
12/15(木) 13:00 - 16:20
東2ホール SuperTHEATER
無料

概要

半導体後工程分野では大きな変革が起きています。2.5D/3D、チップレット、ボンディング技術の進化、RDLなど、アプリケーションによって様々な要求が求められています。業界のグローバルリーダーからパッケージ分野における今後のビジョン、方向性を紹介します。

プログラムアジェンダ

13:00 - 13:30

Challenges and Opportunities in Heterogeneous Integration using Chiplets

Ravi Mahajan
Fellow
Intel

Heterogeneous Integration is a powerful and crucial enabler for the continued growth of computing performance.  Advanced packaging technologies, primarily using chiplets are critical enablers of Heterogeneous Integration (HI) because of their importance as compact, power efficient platforms that define key technology vectors. This talk will focus on the projected evolution of advanced packaging architectures.  Specific examples, showing how product implementations take advantage of these technologies, to provide an unprecedented level of performance, will be used to describe the challenges and opportunities in developing robust advanced package architectures. In addition to performance characteristics, this talk will also illustrate key opportunities and challenges in standardized die-die links e.g. the UCIe specification, materials development, manufacturability, metrologies and reliability.

13:30 - 13:45

チップレット時代における半導体パッケージ革命

折井 靖光
Rapidus 専務執行役員 3Dアセンブリ本部長
APCS実行推進委員会 委員長

最先端の半導体コストが上がっている中、コアやメモリーといったロジックの構成要素を一つのチップ上に混載するのではなく、構成要素を個別に別チップとして製造し、パッケージ基板上にそれぞれ実装するという「チップレット」と呼ばれる技術が大きな注目を集めています。チップ同士をシグナルインテグリティ、パワーインテグリティを考慮した上で、最短で繋げることが要求され、最先端パッケージ技術がIT機器の性能向上の鍵を握っています。

13:45 - 13:50

3DICのマテリアル開発を通じて日本のパートナーと世界の顧客をつなぐ

江本 裕
TSMCジャパン3DIC研究開発センター
バイスプレジデント センター長

本年初開催となる、Advanced Packaging and Chiplet Summitに祝辞を申し上げます。2021年3月に設立し、本年6月にクリーンルームを完成したTSMCジャパンR&Dセンターは、材料科学における次世代の3次元集積化技術や高度なパッケージング技術の研究を推進しています。半導体の材料や基板、装置に強みを持つ日本のパートナーとTSMCの世界の顧客をつなぎ、3D Fabric・3D ICの新たな市場を創出することで、日本の半導体業界に貢献してまいります。

13:50 - 14:20

Collaborations to Drive 3DFabric Innovations with Local Partners

Jun He
Vice President of Quality and Reliability and Advanced Packaging Technology and Service
TSMC

With the development of 3D IC and associated packaging technologies, semiconductor industry has extended performance and density optimization to system level complementary to traditional chip scaling. Amid broader adoption of TSMC’s advanced 2.5D and 3D packaging solutions along with growing chiplet complexity and form factor, the interaction with substrate become increasingly crucial and requires continue innovations on both oS assembly process, substrate layout & fabrication as well as material breakthrough.

With TSMC Japan 3DIC R&D Center, we are establishing a broader collaboration platform with local academia and industry on packaging material and substrate technology development. Our current research focus areas include substrate/packaging layout co-optimization for yield and reliability, new oS bonding technology and materials, enhancing thermal management through design/process solutions and new material development. Our process pilot lines in TSMC Japan 3DIC R&D Center and back in TSMC HQ fabs could also serve as a validation platform to accelerate our partners’ continuous innovations. Our objective is to grow together with our local ecosystem through strategic collaborations and long-term partnership.

14:20 - 14:50

IOWN構想における光電融合デバイス技術

竹ノ内 弘和
NTT
先端集積デバイス研究所
所長

ネットワークとコンピューティング領域に変革をめざすIOWN構想を支える光電融合デバイス技術について概説する

14:50 - 15:20

New Generation Packaging Solutions for Heterogeneous Integration

C.P Hung
Vice President
Corporate R&D
ASE Group

IC Packages are typically flip-chip based with various structures to meet demanding high performance computing needs. This presentation will discuss innovative Fan-Out technologies - FOCoS, FOCoS_B, FOSiP and 2.5D/3DIC, describing how the needs are achieved with higher precision, smaller form factor and enhanced electrical system performance, so very essential for new decade AI server, data center, 5G and automotive computing applications.

15:20 - 15:50

Evolving AI Models and Implications to Semiconductor Technology

Rama Divakaruni
Distinguished Engineer
IBM Research
IBM

The past decade has seen an explosion in compute needs for Artifical Intelligence workloads. AI is now part of many of our day to day experiences and is quite pervasive. This accelerated pace has been fueled by large data crunched by distributed compute systems enabled in the cloud. Concurrently, transistor scaliing has slowed. Hence the resurgence of heterogenous integration and the co-location of memory and logic on AI compute modules. In this talk, we will explore the link between large AI models, newer algorithms, Ai accelerators and their implications to advanced semiconductor technology.

15:50 - 16:20

Supporting the Future of High-Performance Computing

Mark Fuselier
Senior Vice President, AMD Technology & Product Engineering
AMD

Key innovations are required over the next decade to drive the continued scaling of High-Performance Compute (HPC) Capability. As classic Moore's law slows to a crawl, our world's biggest opportunities, from medical research, climate change, and electrical grid efficiency, all rely on our industry to drive scaling essential to HPC. To meet this challenge, the industry will need to focus on areas spanning foundry technology, packaging, design, and system to ensure the perf/Watt and cost scaling necessary to support future HPC scaling.